NXP Semiconductors /LPC11Axx /ADC /CR

Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,…, and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are 0 (as after Reset) channel 0 is selected automatically.

The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.

Burst mode

0 (SOFTWARE_CONTROLLED_): Software-controlled mode: Conversions are software-controlled and require 11 clocks.

1 (HARDWARE_SCAN_MODE_): Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. If bit 20 in this register is set (single-burst mode), hardware clears this bit automatically after one set of conversions on all of the selected channels.

This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).

0 (11_CLOCKS): 11 clocks / 10 bits

1 (10_CLOCKS): 10 clocks / 9 bits

2 (9_CLOCKS): 9 clocks / 8 bits

3 (8_CLOCKS): 8 clocks / 7 bits

4 (7_CLOCKS): 7 clocks / 6 bits

5 (6_CLOCK): 6 clocks / 5 bits

6 (5_CLOCKS): 5 clocks / 4 bits

7 (4_CLOCKS): 4 clocks / 3 bits

Single-burst mode

0 (CONTINUOUS_BURST): Continuous. Burst mode can only be terminated via a software write to clear bit 16 in this register.

1 (SINGLE_BURST): Single-burst. When the burst mode is selected by writing a 1 to bit 16 in this register, the ADC cycles through a single set of conversions on the selection of channels specified in the SEL field. Once the conversion has been completed on each selected channel, bit 16 is automatically cleared and the conversions stop until a new trigger event occurs.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

When the BURST bit is 0, these bits control whether/when an A/D conversion is started. All other values are reserved.

0 (NO_START_THIS_VALUE): No start (this value should be used when clearing PDN to 0).

2 (START_CONVERSION_NOW): Start conversion now.

4 (START_CONVERSION_WHE): Start conversion when the edge selected by bit 27 occurs on ATRG0.

5 (START_CONVERSION_WHE): Start conversion when the edge selected by bit 27 occurs on the analog comparator output.

6 (START_CONVERSION_WHE): Start conversion when the edge selected by bit 27 occurs on ATRG1.

8 (START_CONVERSION_WHE): Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1].

10 (START_CONVERSION_WHE): Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1].

12 (START_CONVERSION_WHE): Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1].

14 (START_CONVERSION_WHE): Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].

This bit is significant only when the START field contains 0100-1110. In these cases:

0 (START_CONVERSION_ON_): Start conversion on a rising edge on the selected signal.

1 (START_CONVERSION_ON_): Start conversion on a falling edge on the selected signal.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.